Traditional layout design has relied on design rules as a model for process capability and a measure of design quality. At highly-scaled technology nodes such as 22 nanometers (nm), many scenarios exist where design rules are inaccurate or inapplicable.
Circuits such as static random access memory (SRAM) bitcells, embedded dynamic random access memory (eDRAM) bitcells (see, for example, J. Barth et al, “A 45 nm SOI embedded DRAM macro for the POWER7™ processor 32 MByte on-chip L3 cache,” Int. Solid State Circ. Conf, (2010)) and latches are highly replicated across the chip making them area and yield critical, while being performance and power critical at the same time. Aggressive designs even at the 45 nm node exist with over 2 million clocked storage elements (latches). See, for example, J. Warnock et al, “POWER7™ local clocking and clocked storage elements,” Int. Solid State Circ. Conf., (2010). The high-density requirements for these circuits make design rules too conservative in highly-scaled technologies. The reason for this is that design rules are developed to cater to arbitrary circuits and layouts. For vertically integrated circuit manufacturers who design the circuits and define and perform manufacturing process steps, all parts of the layout should be customized to the process capability, and the emerging manufacturing process should be customized for the layout. This is a highly specialized and important task to achieve high-performance integrated circuits with higher density and performance requirements. For specialized circuit design companies who utilize other manufacturing facilities (also known as fabrication facilities or fabs for short), such inter-related design/process collaboration exists to achieve best mutual gains both in product performance and cost requirements.
To achieve the best combination of layout and process, very fine tuning of the layout features is required, aided by maximum accuracy patterning simulation checks that account for the variability in the process. Physical design at a macro or global scale has seen much advancement in the last few decades, but this recent challenge of high-density leaf cell design has not received the same attention by the design automation community. See, for example, S. R. Nassif and K. J. Nowka, “Physical design challenges beyond the 22 nm node,” Int. Symp. Phys. Des. (2010).
A similar scenario is seen with the Design Rule Development (DRD) in integrated circuit manufacturing fabrication process, where design and process steps need to be analyzed and formulated interactively to achieve best mutual gains. DRD process defines important ground rules for the circuit designer to achieve circuits and devices with best manufacturability and high performance. Any violation of the design rules set by the manufacturer produces a fatal error that makes the product unusable and worthless costing both to the manufacturing and the designer significant value and resource time. Typical design rules are rules about proximities, overlap ratios, intersection coverage of geometrical shapes defining the integrated circuit devices and structures.
During DRD, the correct design margins for each rule type are being explored. Too large margins sacrifice design space, yielding larger chip area and waste wafer usage. Too small margins risk manufacturability and cause lower yields. Hence the DRD process requires fine tuning layout variants to identify patterning breakpoints which can then be translated into design rules. DRD is an increasingly challenging task at today's advanced technology nodes because of the explosion in number and complexity of design rules.
Both scenarios (high density cell design, like SRAM cells, and DRD process) described above currently require many interactive steps, which involve designer modifications followed by layout simulations for printability analysis for margin checks. During this process, designer know-how in modifying the layout to achieve the performance specifications under design constraints is extremely critical. For instance, typical SRAM cell layouts demand high density and robust electrical performance, and therefore, designers are often allowed to utilize non-rectangular, specially permitted design rule-violating shapes to pack as much into a small cell size as is possible. In other words, they are allowed to violate certain design rules by carefully checking the printability and manufacturability requirements with detailed analysis. With tight area constraints, designs must pack the maximum electrical performance with stringent stability requirements, and still honor the manufacturability constraints. This process is highly interactive in nature. Designers often experiment with new layout shapes, make local modifications and test out some new ideas to trade off performance with stability and/or area. Each layout candidate goes through some performance checks and manufacturability assessment that constitute the bulk of the design time.
Thus, improved techniques for layout design would be desirable.